A communication system (e.g. a system including a transmitter, a receiver and a communicating channel) may handle a large number of bits of data exchange (e.g. gigabits or terabits) per second over several thousands of miles of distance. As communication systems may become more popular (e.g. cell phone, internet, inter-chip or intra-chip communication systems), communication systems with lower cost, smaller size and higher data efficiency may appear in market.
The transmitter and the receiver of the communication system, may need to match their operating characteristics (e.g. synchronize a frequency and/or a phase of a clock) to reliably process (e.g. to reduce a number of faulty bits in a processed data per million bits of a received data stream) an exchanged data stream. For example, in the case of baseband data transmissions, the transmitter may generate the clock signal to control the flow of a transmitted data and the receiver may generate another clock signal with matching characteristics (e.g. the frequency and the phase) to sample the received data at such temporal locations that may produce an optimal data recovery.
The receiver and the transmitter may need to exchange a predetermined pattern of data so that the transmitter and receiver may synchronize their clock signals. Inherent errors in the communication channel (e.g. noise) may create problems in such a scheme. Such a scheme may be difficult to implement and may increase number of components, area, power consumption and cost of the system. Dissimilar synchronization logic in the transmitter and the receiver in a transceiver may further complicate the design and increase the cost.
In future, a rate of data communication between the transmitter and the receiver may increase (e.g. gigabits per second). This may happen because a data processing component (e.g. a Central Processing Unit (CPU)) may be able to process or generate data at a faster rate. Or this may also happen because of the development of a data memory system (e.g. a hard disk) that may need to communicate a high density of data to the data processing unit within a reasonable amount of time.
At the higher rate of received data signal it may be difficult to effectively control data sampling process in the receiver. For example, semiconductor circuits, such as complementary metal oxide semiconductor (CMOS) circuits, may be unable to operate at a sufficiently high frequency to optimally sample the received data stream.
In a time-interleaved design (e.g. multiple slower sampling circuits may operate in parallel in a time skewed fashion to simultaneously sample a high frequency data stream), although a slower sampling circuit may suffice, it may become important to precisely control the time skew (e.g. a phase noise) between time-interleaved units.
While the data rate may increase, a channel bandwidth may remain same. This may increase a distortion that a signal may suffer while propagating through the channel and may reduce the size of an eye opening (e.g. due to a inter-symbol-interference). At the higher rate of data communication, in abscence of a precision timing control technique it may not be possible to obtain and maintain an optimal sampling temporal location.
At the higher data rates it may also become difficult to distribute the clock over an entire integrated circuit (e.g. a transceiver) as the tolerance for a phase noise in the clock may reduce. The precision timing control technique may need to take into consideration all processes of the phase noise in the entire system. So, a precision timing control technique may become complex and may take finite amount of time which, in turn, may make it difficult to maintain overall high speed of data transfer.